A totem pole output is one that is connected through active devices to both sides of the circuit's power supply. Only one of the active devices can be biased on at any given time. When one is on, it effectively connects the output directly to the positive side of the power supply; when the other is on the output is connected directly to the negative side of the supply.
The advantage of totem pole outputs is that they have very low output impedance at both high and low output levels. This results in good noise immunity and the capability for high-speed operation.
A typical output circuit has a NPN transistor with its emitter connected to ground and its collector connected to the positive side of the power supply through a load resistor. When the transistor is biased on, the output is a low impedance to ground just as in the case of the totem pole output. However, when the transistor is biased off, the load resistor is a significant impedance across which noise voltages can be developed. Also, when driving a capacitive load, the load resistor, along with the load, has a time constant which increases the time for the output voltage to build up to its maximum level.
FIG. 1 is a prior art buffer having a totem pole output. The buffer includes an N-type metal oxide semiconductor (NMOS) and a P-type MOS (PMOS) 120 coupled in series between V.sub.cc 130, the voltage supply, and ground 140. The output is coupled between the NMOS 110 and PMOS 120. The gate of the PMOS 120 receives the pull-up signal 150, while the gate of the NMOS 110 receives the pull-down signal 160. Thus, when the buffer is switched from a pull-up to a pull-down, the PMOS 120 is turned off while the NMOS 110 is turned on. Because it takes some time for the PMOS 120 or NMOS 110 to fully turn off, there is a period when both devices are partially on, and this causes a totem pole current.
FIG. 2 illustrates the pull-up signal 210 and pull-down signal 220 for the circuit of FIG. 1. As can be seen from FIG. 2, there is a period when both the NMOS and PMOS are partially on, t.sub.overlap 230, i.e. the gate input to the NMOS is above the threshold voltage, while the gate input to the PMOS is below the threshold voltage. This overlapping period 230 produces a totem pole current. This may result in ground bounce. Ground bounce occurs when the chip ground moves up and down with respect to the PC-board and system ground. This changes the output Low voltage and changes the apparent input voltage, effectively adding to or subtracting from the input threshold voltage. This is disadvantageous because it may cause a false reading, and it increases power consumption. Therefore, it would be advantageous to have an output buffer that did not produce a totem pole current.